Complete semiconductor engineering support, from the first architecture idea to the final layout.
Digital design is a core strength at Ascent Semiconductors, and we cover it end to end. Applying modern methods and trusted tools, our engineers carry a design from analysing the architecture, through developing the micro-architecture, to writing the RTL, so your product starts on solid ground.
Verification is among the areas we are most known for. Using SV/UVM, assertion-based and constrained-random techniques, we work toward designs free of defects. We can take charge of the whole effort, from choosing the methodology and building the environment to closing coverage and final sign-off, whether at IP or SoC level.
Testability is another field we specialise in. Features that make a chip easy to test have to be planned while the chip is being designed, so that production testing stays efficient. We guide clients in building these DFT techniques into their designs, making chips easier to test and cutting test costs.
Our physical design engineers convert logical circuits into a layout that a fab can actually manufacture. Using advanced algorithms and techniques, they balance performance, power and area, taking each design smoothly from idea to silicon so clients end up with high-quality integrated circuits.
Analog design, layout and foundation IP form another major focus. Our engineers handle analog design from the first specification through post-silicon validation, helping clients create strong, high-performing analog circuits for their applications. A separate team dedicated to standard cell and IO design also supports building and characterising cell libraries.
To sum up, our services span digital ASIC design and verification, DFT, physical design, analog design and layout, and standard cell and IO design. Together they help clients create leading-edge designs, lift product performance and reach the market sooner.
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