Digital Verification
Verification is among the areas we are most known for. Using SV/UVM, assertion-based and constrained-random techniques, we work toward designs free of defects. We can take charge of the whole effort, from choosing the methodology and building the environment to closing coverage and final sign-off, whether at IP or SoC level.
What we cover
SV/UVMAssertion-basedConstrained-randomCoverage closureSign-offIP & SoC level
To sum up, our services span digital ASIC design and verification, DFT, physical design, analog design and layout, and standard cell and IO design. Together they help clients create leading-edge designs, lift product performance and reach the market sooner.